1. Field of the Invention
This invention relates to a semiconductor device and method for manufacturing it, for example to a semiconductor memory device including capacitorless DRAM memory cells and a method for manufacturing it.
2. Related Art
A conventional DRAM memory cell of a DRAM includes a capacitor for storing signal charges and a switching transistor (for example, a MOSFET or other FETs). Capacitance of the capacitor required to store signal charges is generally about 30 fF. It is necessary to keep this capacitance of the capacitor of about 30 fF for a DRAM to maintain stable operation, even if the reduced design rule for the DRAM is adopted due to improvement in a degree of cell integration. Therefore, the DRAM memory cell of a conventional DRAM generally have required process improvement for miniaturizing a capacitor, such as thinning an insulating film for a capacitor of stack type or trench type.
On the contrary, a capacitorless DRAM has been proposed. In a DRAM memory cell of the capacitorless DRAM, a transistor (for example, a MOSFET or other FETs) is necessary, but a capacitor is not required. Therefore, the DRAM memory cell of the capacitorless DRAM may have less possibility to hinder improvement in a degree of cell integration.
The field of applications of capacitorless DRAM memory cells includes, for example an embedded device with both a logic device and memory device embedded. It is advantageously possible to realize a large-scale embedded device by adopting capacitorless DRAM memory cells while reducing the number of processes for manufacturing memory cells.
The capacitorless DRAM memory cell has two types of a memory cell, one formed on an SOI substrate and the other formed on a bulk substrate such as a bulk silicon substrate. The memory cell on the SOI substrate is disclosed in Japanese Patent Laid-Open No. 2002-246571, and the memory cell on the bulk substrate such as the bulk silicon substrate is disclosed in “Symposium on VLSI Technology Digest of Technology Paper” by R. Ranica, et al., 2004.
A typical example of the memory cell on a bulk silicon substrate will be described. On the bulk silicon substrate, there typically exist a gate electrode and a gate oxide film which constitute a MOSFET. In the bulk silicon substrate, there typically exist a p-type well (Pwell) under the MOSFET and an n-type well (Nwell) under the Pwell.
The Pwell stores holes which are signal charges. The phenomenon that the threshold voltage of a MOSFET varies depending on whether holes exist or not may be used to realize a memory cell. The Pwell includes the Nwell underneath and STIs on sides thereof, since it is necessary, for each MOSFET (each memory cell) to be isolated from neighboring MOSFETs, that Pwell be isolated for each MOSFET (each memory cell).
An amount of the signal of a memory cell on the bulk silicon substrate δVth is specified in the following expression (1):δVth∝Cpn/Cgate   (1).Where Cgate is the capacitance between the gate electrode and the Pwell, and Cpn is the capacitance between the Pwell and Nwell.
The amount of the signal δVth represents difference between the threshold voltage of the MOSFET in the case of existence of holes and that in the case of nonexistence. The capacitance Cpn between the Pwell and Nwell corresponds to depletion layer capacitance of p-n junction formed by the Pwell and Nwell. The expression (1) above may be transformed to the expression (2) which specifies an amount of the signal of a memory cell on an SOI substrate δVth by substituting the capacitance Cpn between the Pwell and Nwell by capacitance Csoi between the upper portion and lower portion of an SOI insulating film.δVth∝Csoi/Cgate   (2).
Therefore, an increase in the capacitance Csoi may increase δVth, the amount of the signal of the memory cell on the SOI substrate, and an increase in the capacitance Cpn may increase δVth, the amount of the signal of the memory cell on the bulk substrate. For the SOI substrate, the capacitance Csoi due to a BOX oxide film (an SOI insulating film) of a thickness of, for example about 25 nm may allow the optimal amount of the signal δVth to be obtained. However, for the bulk substrate, it is difficult to accomplish the optimal amount of signal δVth, since the amount of the capacitance Cpn is small.